1. Field of the Invention
The present invention relates to semiconductor packages, and, more particularly, to a semiconductor package having a metal pattern layer, and a substrate with a metal pattern layer for the semiconductor package.
2. Description of Related Art
FIG. 1 shows a conventional flip-chip semiconductor package 1. Referring to FIG. 1, a substrate 10 having a dielectric layer 100, electric traces 101 and a solder mask layer 102 is provided, and a semiconductor die 11 is attached on the substrate 10 through a plurality of bumps 111. Then, an underfill 12 is filled between the semiconductor die 11 and the substrate 10 for encapsulating the bumps 111. The underfill 12 binds to the solder mask layer 102 quite well, thereby eliminating delamination of the underfill 12 from the substrate 10.
Electronic products are intended to evolve towards multi-functional, high performance and miniaturized. For a substrate 10 having fine-pitch electrical circuits, the substrate 10 has not only fine-pitch electrical circuits (having an electrical line width of about 12 um), but also large-size grounding portions having a diameter greater than 200 um and electrical circuits having an electrical line width greater than 20 um.
Although the solder mask layer 102 of the substrate 10 can prevent the electric traces 101 from oxidating, the formation of the solder mask layer 102 increases the thickness of the substrate 10 and makes it difficult for the overall structure to meet the miniaturization requirement.
Accordingly, a flip-chip substrate that does not have a solder mask layer is provided. Referring to FIG. 2A, a substrate 20 having a dielectric layer 200, electric traces 201 and a plurality of pads 201a is provided, and a semiconductor die 21 is attached on the pads 201a of the substrate 20 through a plurality of bumps 211. Then, an underfill 22 is filled between the semiconductor die 21 and the substrate 20 encapsulating the bumps 211 to form a semiconductor package 2. The underfill 22 can cover the electric traces 201 to prevent the electric trace 201 from oxidizing.
Furthermore, the substrate 20 has a large-size metal pattern layer 202 formed thereon for improving the thermal dissipation efficiency and providing an electrical grounding for the semiconductor die 21.
However, since the underfill 22 binds to the dielectric layer 200 quite well but to metal materials poorly, if a large contact area exists between the underfill 22 and the metal materials such as the electric traces 201 and the metal pattern layer 202, then underfill delamination is likely to occur.
Accordingly, a semiconductor package 2′ as disclosed by U.S. Pat. No. 7,808,113 is provided. Referring to FIG. 2B, an adhesion promoter layer 203 is formed on the electric traces 201′ and the metal pattern layer 202 of a substrate 20′. Since the underfill 22 binds to the adhesion promoter layer 203 quite well, underfill delamination is thus eliminated.
However, the surfaces of all metal materials except the pads 201a must be roughened to form organometallic surfaces that serve as the adhesion promoter layer 203. Therefore, the fabrication cost and time are increased and the fabrication process becomes more complicated.
Alternatively, the adhesion promoter layer 203 can be formed by depositing a silane coupling agent on surfaces of the metal materials. Since the surfaces of the electric trace 201′ and the metal pattern layer 202 are not even due to, for example, through holes 201b, it is not easy to control the thickness of the adhesion promoter layer 203. In addition, such a fabrication process is also expensive, complicated and time-consuming.
Therefore, it is inevitable that there is a demand to provide a semiconductor package and a substrate for packaging to overcome the above-mentioned disadvantages.